The invention relates to the general field of MOSFETs with particular reference to LDD MOSFETs and with added emphasis on improving power and frequency behavior.
In its most general form, a field effect transistor (FET), located at an active region, consists of a semiconductor substrate (usually silicon) on which is grown a thin layer of insulating oxide (SiO2). A conducting layer (a metal or heavily doped polysilicon) called the gate electrode is deposited on top of the oxide. Two heavily doped regions called the source and the drain are formed in the substrate on either side of the gate. The source-to-drain electrodes are equivalent to two PN junctions back to back. This region between the source and drain regions is called the channel region. The gate electrode can control the flow of current from source to drain by varying the amount of charge present in the channel region.
When power is not a concern, the most economic layout for FETs is for source, gate, and drain to all lie in the same plane. When the device is required to operate at high power, means must be found for dissipating the generated heat, particularly at the source. To accomplish this, the design illustrated in FIG. 1 has been widely adopted in the industry. In this design, connection to the source is made through lower area 11a which occupies the entire bottom of the device, where it can be directly connected to a heat sink. Lower area 11a is connected to source 11b through sinker 12. Both 11a and 12 are of P+ silicon because Pxe2x88x92 region 18n needs to be grounded and metallic shorting bar 13 is provided in order to connect 11b to 12. The remainder of the device is of a standard nature. Gate 14 controls the current flow in the body of the device 18, across channel region 15, into the drain which is made up of an inner, lightly doped section 16 and an outer, heavily doped section 17.
FIG. 2 shows the equivalent circuit of the design seen in FIG. 1. In addition to the series resistance Ra and Rd associated with the source and drain respectively, three parasitic capacitances can also be seen. These are the source-gate capactiance Cge, the drain-gate capacitance Cdg, and the source-drain capacitance Cde. Of these, Cde is the largest and most important in terms of determining frequency response of the device.
Unfortunately, Cde is large in designs of the type shown in FIG. 1 because of the relatively thin depletion layer that forms at the N+/Pxe2x88x92 interface. One approach that has been used to overcome this problem has been the design illustrated in FIG. 3. Here, dielectric layer 33 is inserted between the source, drain and channel regions 11b, 16/17, and 15, respectively. This ensures that the magnitude of Cdg will be determined by the thickness of 33 rather than by any depletion layers. While this approach is effective in greatly reducing Cde, it has the unfortunate side effect of blocking the flow of heat from the source area 11b down to the heat sinking area 11a. Thus, devices of the type shown in FIG. 3 are generally limited to operating at low power levels.
A routine search of the prior art was performed but no references that teach the exact processes and structures of the present invention were discovered. Several reference of interest were, however, encountered along the way. For example, in U.S. Pat. No. 5,554,546, Malhi shows a xe2x80x9cpartial SOIxe2x80x9d LDMOS with oxide under the channel, drain and source. In U.S. Pat. No. 5,930,642, Moore et al. describe a LDMOS with oxide under the channel. In U.S. Pat. No. 5,650,354, Himi et al. show a SIO LDMOS without oxide under the Tx. Pein (U.S. Pat. No. 5,382,818), Pein (U.S. Pat. No. 5,378,912), and Yamaguchi et al. (U.S. Pat. No. 5,777,365) all show various LDMOS devices with different oxide layer configurations.
It has been an object of the present invention to provide a LDMOSFET design that has both good high performance characteristics and good power dissipation.
Another object of the invention has been to provide a method for manufacturing said improved LDMOSFET.
These objects have been achieved by using a partial SOI (silicon on insulator) approach. In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker, but this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain structure (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap of the lightly doped section. The structure is described in detail together with a process for manufacturing it.